1. Field
Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a method for forming fine pattern of a semiconductor device by using spacer patterning technology.
2. Description of the Related Art
As the integration degree of semiconductor memory devices increases, the size of semiconductor devices becomes smaller and smaller. Accordingly, the sizes of the circuit patterns of the circuits that constitute a semiconductor device are reduced and are reaching physical limits in terms of exposure processes for forming a mask for transferring a pattern onto a semiconductor substrate or wafer.
However, since upgrading a mask to overcome the limitations in optical definition increases equipment prices and production costs, methods that form fine pattern while addressing the above-discussed features in a conventional mask process are useful.
An example of such a method is Spacer Patterning Technology (SPT) where spacers are formed over a semiconductor substrate and a patterning process is performed on a layer by using the spacers as a mask. Since pattern is formed to have a line width determined depending on the thickness of the spacers according to the spacer patterning technology, the limitation in optical definition is overcome using exposure equipment of argon fluoride (ArF) or krypton fluoride (KrF) and fine pattern, for example, patterns as fine as approximately 30 nm or less may be realized on a substrate.
Here, the spacer patterning technology uses an additional mask process while not requiring an upgraded mask.
In other words, since the spacers are typically formed on the sidewalls of pattern, a line-type partition, which is a sacrificial layer pattern for forming the spacers, is formed and also, since the spacers is formed with a rim shape on the sidewalls of the partition, the spacers are selectively removed and cut for isolation of the pattern, and the pattern is formed to have different line widths in a cell region and a peripheral circuit region. As such, a total of three masks are used: one mask for forming the partition, another mask for cutting the spacers, and the other mask for forming pattern in the peripheral region.
When the mask for cutting the spacers and the mask for forming the pattern in the peripheral region are used separately, an etch equipment is additionally used other than mask equipment. Moreover, a hard mask has a higher etch selectivity than a pattern target layer. More specifically, the hard mask has a stacked structure to realize fine pattern of a desired line width. For example, when the fine pattern forms trenches for device isolation, the hard mask for forming the fine pattern of a desired line width has a stacked structure where a first amorphous carbon layer (ACL) 210 of approximately 1500 Å, a first silicon oxynitride (SION) layer 220 of approximately 300 Å, a polysilicon layer 230 of approximately 400 Å, a second amorphous carbon layer (ACL) 240 of approximately 1500 Å, a second silicon oxynitride (SiON) layer 250 of approximately 300 Å, and a bottom anti-reflection coating (BARC) layer 260 are sequentially stacked over a semiconductor substrate 200. Subsequently, a partition-forming photoresist pattern 270 for forming spacers is formed as illustrated in FIG. 1.
Here, although the first amorphous carbon layer 210 and the second amorphous carbon layer 240 are each have a higher etch selectivity than the pattern target layer, they can be costly to manufacture. Therefore, when two or more amorphous layers are formed, production costs increase.